TSMC CEO Tells Shareholders It Will Be 'A Long Time' Before AI Chip Demand Can Be Met
News Summary
On June 4, 2026 (Taiwan Standard Time, UTC+8), TSMC CEO C.C. Wei addressed shareholders at the company's annual general meeting in Hsinchu, Taiwan, and delivered a frank assessment of the semiconductor industry's most defining challenge: the world's most advanced chip foundry cannot keep pace with AI-driven demand, and the gap will persist for years.
TSMC CEO's Warning at the 2026 Annual Shareholders' Meeting
At the annual general meeting on June 4, 2026 (Taiwan Standard Time, UTC+8), C.C. Wei told shareholders directly: "It will be a long time before we can meet customer demand." The statement confirmed what supply-chain analysts had long been flagging — demand at leading process nodes (sub-5nm and sub-3nm) is expected to exceed available manufacturing capacity by 25–30% throughout 2026, and meaningful relief is not projected until at least 2027.
Wei also addressed pricing strategy, pledging that TSMC would avoid the kind of abrupt price hikes that shook the memory chip market in previous cycles. Maintaining supply stability and long-term customer relationships, he said, takes priority — a message aimed at major customers including NVIDIA, Apple, AMD, and Broadcom.
The CoWoS Advanced Packaging Bottleneck
Beyond raw wafer output, the tightest choke point in the AI chip supply chain is advanced packaging — specifically TSMC's CoWoS (Chip on Wafer on Substrate) process. CoWoS is the technology that stacks high-bandwidth memory (HBM) alongside logic dies in a single compact module, and it is the architectural foundation of every modern AI accelerator: NVIDIA's H100, H200, and Blackwell GPUs all depend on it.
TSMC has been scaling CoWoS aggressively, expanding from roughly 35,000 wafer-equivalents per month in late 2024 to a projected 130,000 by the end of 2026 — nearly a fourfold increase in under two years. Yet the expansion still falls short of demand: CoWoS allocation is sold out through all of 2026. NVIDIA alone holds more than 60% of total available CoWoS capacity. The downstream consequences are visible across the industry. Google has reportedly trimmed its 2026 TPU (Tensor Processing Unit) production target by approximately 25% because of packaging constraints, illustrating how a single manufacturing bottleneck can cascade across the entire AI computing ecosystem.
Record Financial Results Reflect Structural Demand Pressure
TSMC's own financial results illuminate the scale of the demand overhang. In Q1 2026, the company reported revenue of NT$1.13 trillion (approximately US$35.7 billion), a 35% year-over-year increase driven almost entirely by orders for AI-capable silicon. The company projects full-year 2026 revenue growth of more than 30% in US-dollar terms — among the strongest growth rates in its corporate history.
To address the capacity shortfall, TSMC has committed to capital expenditure of US$56 billion in 2026, a record figure. The investment is directed at expanding 3nm fabrication capacity, ramping 2nm production, and building advanced packaging infrastructure across facilities in Taiwan, the United States, Japan, and Europe.
Broadcom Echoes the Capacity Warning
TSMC is not alone in raising the alarm. Broadcom, a leading designer of custom AI accelerators for hyperscale cloud providers, has warned that constrained foundry capacity will limit its ability to fulfill AI chip orders well into 2026. Broadcom's supply chain team is now competing to secure multi-year capacity agreements with TSMC — a reflection of how chipmakers must compete on manufacturing access, not just chip design.
The supply pressure has also pushed major cloud providers — Microsoft, Google, Meta, and Amazon — to accelerate development of in-house AI silicon as a hedge against a supply chain that remains structurally undersupplied.
Why Leading-Edge Chip Manufacturing Is So Difficult to Scale Quickly
The current shortage reflects deep structural realities of advanced semiconductor manufacturing. Building a leading-edge fabrication plant requires three to five years from groundbreaking to volume production. Critical equipment — such as ASML's extreme ultraviolet (EUV) lithography systems — is produced in very limited annual quantities and must be ordered years in advance. Advanced packaging technologies like CoWoS are now considered as complex and capital-intensive as wafer fabrication itself, requiring highly specialized tools and deeply trained engineering teams.
These long lead times mean that even record-level investment cannot produce supply relief quickly. The semiconductor industry inherently operates on multi-year development cycles that are structurally mismatched with the speed at which AI model complexity and deployment scale have grown since 2023.
Implications for the Broader AI Technology Landscape
The sustained supply shortage carries significant implications for the wider AI industry. Data center expansion timelines will remain constrained, limiting how quickly cloud providers can scale AI training and inference infrastructure. Chip allocations will continue to favor the largest buyers, making it harder for mid-sized AI companies and enterprises to secure adequate compute resources. This dynamic is accelerating research into more compute-efficient model architectures — including quantization, model compression, and mixture-of-experts designs — that can deliver strong performance with fewer chips.
Longer term, TSMC's ongoing capacity investments, combined with parallel build-outs at Intel Foundry Services and Samsung Foundry, are expected to progressively narrow the supply gap after 2027. The era of abundant AI silicon is coming, but the manufacturing infrastructure required to support it is still being built — one fab, one packaging line, and one EUV machine at a time.